The present invention relates to semiconductor fabrication, and in particular to dual damascene interconnects formed in a hybrid dielectric and methods for fabricating the same.
In the fabrication of semiconductor devices, the size of semiconductor devices has been continuously reduced in order to increase device density. Accordingly, multiple layers may be required to provide a multi-layered interconnect structure. A typical process for forming a multi-layered interconnect structure is a dual damascene process. In the dual damascene process, via openings are first anisotropically etched through an inter-metal dielectric (IMD) layer by conventional photolithography and etching. A second anisotropically etched opening referred to as a trench opening is then formed overlying one or more of the via openings by second photolithography and etching. The via openings and the trench opening together make up the dual damascene structure, subsequently filled with metal followed by CMP to planarize the wafer process surface in preparation for formation of another overlying layer or level in a multi-layered semiconductor device.
In order to lower the RC of the semiconductor device and improve its performance, low k dielectric layer have been increasingly investigated. Low k dielectric materials, however, present a more difficult to control etching profile than high k materials and may be damaged in a conventional dual damascene.
U.S. Pat. No. 6,521,524 to Wang et al. discloses a via filling dual damascene process using a middle stop layer. In this method, however, a drawback is susceptibility of low-k materials to etching damage during removal of stop layers, whereby low-k materials may be damaged by overetching to detrimentally alter etch opening profiles as well as degrading dielectric constant properties. The various problems included in interconnect formation processes with low-K materials are exacerbated in higher aspect ratio openings and in dual damascene formation processes where multiple etching steps are conducted in the manufacturing process.
Thus a need exists in the integrated circuit manufacturing art to develop a more robust dual damascene interconnect whereby etching damage to low-K material is reduced, while electrical and mechanical properties of the interconnect are improved, thereby improving device yield and reliability.